How Huawei plans to take on its rivals with a chip design breakthrough
Shanghai, May 29
,: China's electronics giant Huawei is using a new principle for its chip designing framework that focuses more on cutting transmission time than shrinking transistors. The company plans to use innovative technologies like LogicFolding based on this principle to continuously compress signal propagation delay and improve transistor density.
The current chip design framework rests on Moore's law which dates back decades when Intel co-founder Gordon Moore posited in 1965 that the number of transistors on a microchip will double every two years.
The Tau Scaling principle could be a revolutionary step in the future of chip designing as it shifts focus from geometric scaling to time scaling. The principle that governs modern advanced chips is to shrink the size of transistors to fit onto a microchip. But this mechanism may have a handicap. It may not be easy to shrink them beyond a point. This is where time scaling becomes useful as it makes cutting signal transmission time the underlying principle of future chip designs.
The innovative core technologies like LogicFolding, which Huawei will use for its Kirin chips scheduled to launch in Fall 2026, will work on the Tau Scaling principle in order to drive up performance, energy efficiency, and transistor density.
"With the t Scaling Law, we look forward to working closely with scientists, engineers, and industry partners around the world to drive the sustainable development of the semiconductor and electronics industries," Huawei's semiconductor chief He Tingbo noted.
Huawei's new chip design breakthrough will help the chip maker to sidestep the US sanctions that restrict access to advanced lithography machines from ASML.
By 2031, Huawei is aiming for high-end chips based on the t Scaling Law that are expected to feature a transistor density that is equivalent to 14 A (1.4 nm) processes.
"This is a breakthrough for Huawei, but it's not a threat for TSMC," Reuters quoted Nvidia CEO Jensen Huang, who was in Taipei on Thursday.
"TSMC has been using die stacking and 3D packaging for how long now? Almost 10 years. And so TSMC's technology is very advanced," he added.
A Reuters report mentioned Bernstein analysts cautioning in a note that while stacking multiple chip layers boosts transistor density, there's risk of increasing power density and overheating chips.
— ANI
Reader Comments
Honestly, as an Indian, I watch this with mixed feelings. While China's tech advancements are impressive, the US sanctions have pushed them to innovate faster. India also needs to ramp up its own semiconductor ecosystem. We can't rely on imports forever. Hope our government and companies like Tata are taking notes! 🇮🇳
Jensen Huang's comment is spot on. TSMC has been doing die stacking for years - that's their strength. Huawei's breakthrough seems more like a clever workaround rather than true innovation. And Bernstein's warning about overheating is real. Stacking layers creates thermal issues. Still, competition is good for everyone.
Arre yaar, this is what happens when you put sanctions on a determined country! Huawei is literally rewriting the rulebook. But we need to be careful - China's chip industry is advancing rapidly while India is still struggling with basic fab plans. We should learn from their strategy of investing heavily in R&D despite restrictions.
A different perspective: shifting to time scaling instead of size scaling makes sense from a physics standpoint. Transistors can only get so small before quantum tunneling becomes a problem. Huawei is basically saying "let's optimize the whole system instead of just the parts." Smart thinking, but will it be cost-effective for mass production? That's the real question.
I appreciate the innovation, but let's be honest - 1.4nm by 2031? That's a big claim. TSMC and Samsung are already racing towards 2nm and 1.4nm nodes. Huawei is late to the party
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